LCB #2. ONE-GATE WONDERS, Part 1

Some of the handiest circuits around are those that can be made with a single gate.    

                                                                                                                                                         Timers, oscillators, one-shots, pulse stretchers and more can built with just a few components.  The fundamental reason that we can do this is that CMOS outputs swing close to rail-to-rail, while the input switching threshold is, conveniently, about 1/2 the supply (more typically in the range of 1/3 to 2/3 Vdd).  With other logic families, such as olde TTL,  this was not the case and One-Gate Wonders did not work well.

For starters, look at a simple circuit made with an RC circuit and a CMOS inverter. Please see Figure 1.  I show an inverter here, but you could use any kind of gate; for example you could use one input from a NOR gate or an AND gate.  The concept remains the same.

This circuit takes a long pulse and generates a short pulse at the rising edge.  In other words, it differentiates (sort of, at least) the input pulse and produces a short pulse, or "spike", which is independent of the length of the input pulse.

When the input goes HIGH, the voltage at C also goes HIGH by the same amount ("The voltage across a capacitor cannot change instantly"). The output immediately goes LOW.  The charge on the capacitor then decays through the resistor according to the RC time constant.  Eventually the voltage at C will fall  below the switching threshold of the inverter, and the output will go HIGH again.

In this case, the time constant is 33 usec;  we don't know what the exact threshold voltage is, but it is somewhere around 1/2 the supply voltage.  Since this voltage is not that different from  what the voltage will be at point C after RC seconds have gone by, you can crudely (but quickly and conveniently) estimate that the output pulse width will be--guess what-- RC seconds!


The truth is, unfortunately, that you can never be sure what the CMOS threshold will be.  It is a  percentage of the power supply, but it will vary from part-to-part and with temperature.  Therefore, the actual pulse length may be much different than RC seconds  In fact, it could range from about (1.2)RC  to about (0.3)RC.  Most of the time, however, it will be in the neighborhood of (0.7)RC.

This circuit is very handy when you want to trigger something which requires a sharp trigger pulse, such as a 555 one-shot. Or, when the ON time of a pulse is too long and you need a short pulse to save power in a load or reset a circuit.

I know this is a lot of babble about a pretty simple circuit.  So, if you have something better to do, I understand.  On the other hand, if you would like to know some interesting, down and dirty details, stick around:

First of all, somewhere out there is a curious, conscientious person who is wondering exactly what happens when the input goes negative.  This type of person is usually a real pain, but I guess I can't duck the question -even though I would like to do so because the answer is messy.

After the input has been high for a while, the capacitor charges to a voltage equal to the supply.  Then, when the input goes LOW, point C will also (try) to go LOW due to the action of the capacitor .  Again, "The voltage across a capacitor cannot change instantly".  If point C was not connected to a gate leg, the voltage at this point would swing negative, below ground, to a value equal to the supply voltage.  However, the CMOS input is connected to the cathode of an internal "protection" diode whose anode is connected to ground.  This diode will clamp point C to about -1/2 V, preventing it from going any further below ground. See Figure 2.

When the input goes LOW after going HIGH, whatever is driving the input (typically another logic element) must sink a lot of current as the capacitor discharges through the protection diode.  In fact, there is actually a short circuit, for a brief time, while current flows out of the input.  This is where it gets a little messy, because engineers don't like short circuits.  In fact, we don't like any situation, such as this one, where things are undefined.  This is an undefined case because this discharge current is not limited by an actual resistor; instead, it is limited to whatever current can be sunk by the device that is connected to the input.

We must be careful that this current  is not great enough to destroy the input protection diode, which has a maximum rating of 10 MA.  Unfortunately, that's all the CMOS data sheet says; we don't know if this is the average or peak current.  If the input is driven by the output of another CMOS gate, for example, the current will be limited to the short-circuit current that the output of the gate can sink. A standard CMOS output can only sink several MA when the supply is 5 V.  However, at higher supply voltages and lower temperatures, the output current may exceed 50 MA (check the datasheet).  This current clearly exceeds the 10 MA rating of the protection diode.  So, what do we do?  Fortunately, we can usually select small capacitor values which will limit the duration of the overcurrent.  With a .01 uFd cap and a 15 V supply, since I = C*dV/dT and I = 50 MA, the protection diode will be conducting for only about 3 usec.  This is a very short period and it is extremely unlikely that the diode will be damaged - especially if the frequency of operation is low and, thus, the average diode current is small.  On the other hand, if you used a 0.1 uFd capacitor, operated at 15 V, and switched at a frequency of 10 KHZ, the peak current would be 50 MA and the average diode current would be 15 MA and the diode would be subject to failure.  (Caution:  an extremely high-current reverse-voltage pulse, even if very short, can cause CMOS to "latch up" and fry.)

Conclusion?  This is a great circuit, but the subtle failure mode discussed above is sometimes ignored by people who don't read this blog. A discussion:

1.  If you operate at 5-6 VDC supply, don't worry about anything.

2.  At higher supply voltages, if your frequency of operation is less than a few KHz and your capacitor is less than .01 uFd, you should be OK.

3.  At higher supply voltages, if the capacitor and frequency are large, you better be careful.  Keep the capacitor very small (<.001uFd) or put a 1K or 2K series resistor right at the gate input to limit the current.  Note that this resistor will, however, decrease noise immunity somewhat.

4.  And what about the resistor?  It must be large enough so the driving circuit is not loaded down.  So, if a CMOS gate's output is driving the differentiator, better keep it greater than 22K if the supply is 5V.  At greater supply voltages, you can use 10K or so.  As far as a maximum value, the resistor must be small enough so that gate input current, diode leakage, board leakage, etc. will not drag the input HIGH. So, if you are running a circuit near room temperature in a clean and dry location, you can use 10 Meg or even  more without concern.  At high temperatures, or if you might have schmootz or moisture around, you better use 1 Meg or less.

5.  And what about  the pulse length?  You can make RC as short as a few usec, and this should be long enough to trigger things, reset something, etc. However, people who spend too much time at the bench know to make a pulse as long as possible. That way you will be sure that it will do its job, and, almost as important, it is simply easier to find and see on an oscilloscope during development or troubleshooting.

6.  Don't forget that this circuit, and any circuit, will load whatever is driving it.  When the input to the differentiator goes HIGH, the driving device is loaded only with the resistor.  However, when it goes LOW it sees the capacitor connected, essentially, to ground.  This will slow the fall time of whatever is driving the gate.  Therefore, be careful if you must use this node for anything else.

7.  This and similar circuits will work best if the gate has a Schmitt-trigger input. You will have a snappier output, with better rise time and better noise immunity.

And finally, there is still more to talk about.  Is this circuit better than a one-shot?  If so, why?  Who knows?  Who cares?   You'll find out on One-Gate Wonders Part 2, on Larry's Circuit Blog.

.                                                                                                                                                     

LCB #1. HOW TO LIVE WITH CONTACT BOUNCE

Contact bounce is a subtle problem that can lead to unreliable circuit operation.                                  

                                                                                                                                                         Switches and relays all have one thing in common: electrical contacts that make and break a circuit. Contacts have mass, of course, and at least one of the contacts is usually mounted on a springy strip of metal so that it provides “wiping” action and allows overtravel.

Some simple things aren't so simple......Because the moving contacts have mass and springiness, they will bounce as they make and break. For example, when a SPST normally-open pair of contacts is closed, the contacts will come together and bounce off each other several times before finally coming to rest in a closed position. This is "contact bounce". See Figure 1. Note that contacts can bounce on opening as well as on closing, but bounce is usually much worse upon closing.  However, NEVER assume that contacts don't bounce when opening.

The duration of the bounce will vary depending of the design and physical variables of the device. A small, high-speed reed switch, for example, will settle in a few milliseconds; a large contactor may take 10 ms or more. With some switches, such as cheap doorbell buttons, the “human factor” may result in erratic opening and closing as long as a person is touching the button.

The Problem
If you want your switch or relay to simply turn on a lamp or a motor, then contact bounce is usually not a problem. But if you are using a switch or relay as input to a counter, toggle flip-flop, one-shot, or similar device, then you must consider contact bounce. This is necessary, of course, because a digital circuit can respond in microseconds. For example, suppose you want to count widgets as they go by on a conveyor belt. You could set up a mechanical arm that activates a switch at the input of a digital counter. What you might see is that the first widget produces a count of 12, the second widget produces a count of 21, and so on. This would occur because the contacts bounce each time the switch is activated.

The Wrong Solution
There are several ways to solve the problem of contact bounce (that is, to "debounce" the input signal). A common debounce circuit for a switch is shown in Figure 2A. It attempts to use an RC delay to swamp out the bounce from a N.O pushbutton. Resister R1 is the pullup resister. R2 and C1 are chosen so that the time constant is longer than the expected bounce time. An R x C value of about 0.1 seconds is typical. An inverting buffer follows the switch to produce a sharp transition.

 The above circuit is often used; however, it does NOT provide protection against contact bounce. Even if the RC time constant is made extremely long, it is always possible that a particular sequence of bounces will cause the voltage at B to fall and then rise, crossing the voltage threshold and producing a spurious output pulse. Even a slight wiggle of a fraction of a millivolt is enough to cause a rogue pulse.  See Figure 2B.

 


The Correct Solution
For this circuit to work reliably, you MUST use a Schmitt Trigger buffer or gate; one that includes hysteresis. An inverter with input hysteresis will output a LOW when its input exceeds a certain threshold.   However it will not go HIGH until the input drops to a second, lower threshold.  Gates with hysteresis have "snap" action and are invaluable for eliminating spurious pulses when an input is noisy or "squaring up" a signal that changes very slowly.  A CMOS gate such as the 4584 inverter has a hysteresis voltage (the difference between the two thresholds) of about 7-10% of the supply.

By adding hysteresis as in Figure 3A, you can guarantee reliable operation by choosing a time constant large enough so that the ramp time from the lower threshold to the upper threshold exceeds the longest time period that will ever exist between two bounces. In this way, the inevitable transitions that occur during the bounce interval cannot produce a spurious output pulse. See Figure 3B.

The voltage at point B produces a HIGH transition when it drops below the lower threshold. However, even if it rises again due to bounce (as shown), with the addition of hysteresis the output will not go LOW unless the voltage at B rises all the way past the upper threshold and then drops below the lower.  By incorporating a suitable time delay, this cannot occur.  


Another Good Solution
A second debouncing approach is shown in Figure 4.  It requires a SPDT (“form C”) switch, but it provides reliable switch interfacing without the debounce delay required with a SPST switch. It uses a cross-coupled latch made from a pair of NAND gates, an SR flip-flop, or other gate combinations.

If the switch is in the upper position, Q must be high since one of gate A’s inputs is LOW. Since both of gate B’s inputs are HIGH, not-Q must be LOW. The flip-flop will be stable in this state, even if the upper switch contact should be broken.

However, if the switch wiper touches the lower contact, not-Q is forced high. Now both of gate A’s inputs are HIGH, so Q goes LOW and, in turn, not-Q goes HIGH.. The flip-flop is, again, in a stable state and will remain in this state until the upper switch contact is made again.

Because of this bi-stable characteristic, switch bounce has no effect. If noise should produce a temporary LOW on the HIGH input, the flip-flop will not change state because the other input is held LOW with the switch contact; this prevents the flip-flop from changing state.  IMPORTANT: Note that such a noise pulse will be seen as a temporary HIGH on one output; this may cause an error. For this reason it may still be necessary to filter and otherwise condition the input lines.

CAUTION: This paper discusses contact debouncing, but it does not address two absolutely crucial aspects of interfacing to switches and similar devices. One concerns the need for adequate current and voltage so that the switch contacts remain “clean’ and free of oxides and insulating films. The second issue relates to the need to provide protection against noise and destructive transients that can be coupled to inputs. The circuits described here are only suitable for operation with very low current, “dry” switches such as reed, keyboard, or small “tactile” switches; also, these must be located very close to the circuitry to minimize noise problems. Toggle switches or pushbuttons must have gold contacts and be rated for very low power, such as “0.4 VA”. Typical logic voltages and pull-up resistors will not provide enough voltage and current for reliable operation of switches with higher ratings, such as “6 A, 120VAC”. These switches have contacts which are prone to oxidation, and low voltages and currents may not burn through the insulating oxidation layer if the switch has not been operated for a long time.

Stay tuned to Larry's Circuit Blog for a future discussion of interfacing to switches, contacts, and other real-world input devices.